In this article, we will introduce the AXI protocol which is a high performance, high bandwidth, low latency interconnect for high speed communication between components on the same chip. The AXI protocol is based on a point-to-point interconnect to provide high-speed data transfer between the master and slave components. The AXI protocol is designed to support multiple masters and multiple slaves, and it is widely used in many modern SoC designs.
Introduction
In AXI protocol, we have 5 groups of signals:
- AR: Read request
- R: Read response
- AW: Write request
- W: Write data
- B: Write response
With these signals, we are able to build a flexible connection between master and slave components.
AXI wave analysis
This section let’s take a look at a specific AXI bus protocol wave form, let’s first analyze the read burst operation
Here we have 4 burst request, the address are incremental, arlen = 0xF which means that we have 16 burst for each of the transaction, arsize = 0x2means that for each burst, the size is 4bytes, and arburst = 0x1 means that the address is incremental when burst. We can observe that the start addr is not aligned, according to AXI protocol, the first transfer would be 3 bytes.
After several delay, the slave gave out response and read data:
Let’s expand the read data, we can observe that when master & slave have a handshake (valid & ready signal to high), the data is transferred successfully, and when it reaches 16 burst, rlast will be pull up to indicate the last transaction.